The present invention relates to a signal-level converter, particularly, provided between logic circuits operating at different supply-voltage levels.
Any systems installing CPU (Central Processing Unit.), usually, contain a lot of bus (signal) lines through which data are transferred between CPU and peripheral devices connected to the bus (signal) lines, like branches.
Micro-fabrication processes and/or low power supply allow for low CPU power consumption which may otherwise become higher as CPU processing speed becomes higher.
On the contrary, low power consumption has not been achieved enough so far for the peripheral devices connected to CPU, such as, buttery-powered devices; for compatibility with other devices. Such buttery-powered devices are, for example, mobile phones and PDA (Personal Digital Assistant).
There is a strong demand for low CPU power consumption for long use of buttery-powered devices. Such demand, however, cannot be met due to the necessity of compatibility of bus-connected peripheral devices.
Signal inputs at voltage level different from supply-voltage level could cause increase in system current consumption, device malfunction or device damages.
Level-converting integrated circuits are thus required to meet such demand, such as, a 2-power-level converter, shown in FIG. 20.
A system 1, such as PDA, shown in FIG. 20 is equipped with a VccA circuit 2 operating at a supply-voltage level A and a VccB circuit 3 operating at a supply-voltage level B.
In detail, the system 1 is equipped with a first input buffer 5, a first (A to B)-logic circuit 6, a level shifter 7 for supply-voltage-level conversion and a first output buffer 8, for signal transfer from terminals A1 to B1, as shown by an arrow 4.
The system 1 is equipped further with a second input buffer 11, a second (B to A)-logic circuit 12 and a second output buffer 13, for signal transfer from the terminals B1 to A1, as shown by an arrow 10.
The signal-transfer operation is switched by a control circuit 9. In detail, the control circuit 9 switches signal transfer shown by the arrows 4 and 10, in response to a direction-switching signal at a terminal DIR and an operation signal at another terminal *OE. The sign “*” for a signal *OE means that the signal has been inverted.
The known system shown in FIG. 20 operates at two supply-voltage levels VccA and VccB (VccA<VccB). For example, the VccA circuit 2 operates at a supply voltage of 2.5 volts for signal transfer from the terminals A1 to B1 whereas the VccB circuit 3 at a supply voltage of 3.3 volts for signal transfer from the terminals B1 to A1.
In signal transfer from the terminals A1 to B1, a signal input at the terminal A1 is supplied to the level shifter 7 through the first input buffer 5 and the first (A to B)-logic circuit 6. The input signal is subjected to level conversion from VccA to VccB at the level shifter 7, thus a VccB-level signal being output at the terminal B1.
The level shifter 7 is provided for completely turning off P-channel transistors in the first output buffer 8. If the level shifter 7 is not provided, however, gate-to-source voltages Vgs will not become 0 volts for the P-channel transistors, thus the transistors remaining on unchanged, and hence suffering from static currents passing therethrough.
On the contrary, such level shifter is not necessary between the second (B to A)-logic circuit 12 and the second output buffer 13, for signal transfer from the terminals B1 to A1. In other words, an signal input at the terminal B1 is converted into a VccA-level signal at the terminal A1 through the second input buffer 11, the second (B to A)-logic circuit 12 and the second output buffer 13.
Operation of the known system (FIG. 20) will further be explained with reference to FIG. 21.
In FIG. 21, the terminals A and B will be in a high-impedance state when the terminal *OE is set at a VccB level. On the contrary, the terminals A and B will become the input and the output terminals, or vice versa when the terminal *OE is set at a ground (GND) level.
Moreover, the terminals A and B will become the input and the output terminals, respectively, when a terminal DIR is set at the VccB level. Contrary to this, the terminals A and B will become the output and the input terminals, respectively, when the terminal DIR is set at the GND level.
Explained blow is an operation of the known system when an input signal is supplied at the terminal A and output at the terminal B (i. e. *OE=GND, DIR=VccB).
When a VccA-level signal is input at the terminal A, the VccA-level appears at a node α to turn on an N-channel transistor N1 and a P-channel transistor P2 while an N-channel transistor N2 is turned of and hence a P-channel transistor P1 is also turned off, thus a VccB-level signal appearing at a node β.
The VccB-level signal is output at the terminal B through the first output buffer 8, thus level conversion from the VccA to VccB being enabled.
Nevertheless, the level shifter 7 in the first known two-way system consists of several components, thus the system becoming bulk in chip size.
Moreover, signal transfer from the terminals A to B, or vice versa, is decided under the input of a direction-switching signal at the terminal DIR, which causes complexity of control.
Not only the two-way system shown in FIGS. 20 and 21, but also a one-way system shown in FIGS. 22 to 24 is a bus system operating at different supply-voltage levels.
The second known one-way system will be explained with reference to FIGS. 22 to 24.
The one-way system has the same circuitry as the two-way system except that the former has no terminal DIR for supplying a direction-switching signal.
Elements in the second known one-way system that are the same or analogous to the elements in the first known two-way system are referenced by the same reference numerals and will not be explained.
The operation of the one-way system shown in FIG. 22 is the same as that in signal transfer from the terminals A to B, or vice versa in the two-way system.
The one-way system with no terminal DIR is simple in control compared to the two-way system, but, still complex in circuitry, thus being bulk in chip size the same as the two-way system.
A known one-way system performs level conversion with an N-channel transistor only, as shown in FIG. 23. A signal input at a terminal A connected to a first logic circuit operating at a first supply-voltage level is converted for its voltage level by a level shifter 7 through input buffer and (A to B)-logic circuits (not shown). The level-converted signal is then output to a second logic-circuit operating at a second supply-voltage level via a terminal B.
The control circuit 9 supplies a control signal to the gate of an N-channel transistor N1 in the level shifter 7, based on a *OE signal input via a terminal *OE.
In detail, a VccB-level *OE signal input at the terminal *OE turns off the N-channel transistor N1 to isolate the terminals A and B from each other. On the contrary, a GND-level *OE signal allows signal transfer between the terminals A and B.
The operation below is performed when the terminal B is switched to the VccB level from the GND level whereas the terminal A is held at the GND level while the N-channel transistor N1 is on in response to the GND level at the terminal *OE.
A VccB-level signal input to the terminal B is transferred to the terminal A via the N-channel transistor N1 that has been turned on due to the supply of a VccB-level signal to the gate, thus a (VccB−VthN)-level signal appearing at the terminal A (VthN being a threshold level of the transistor N1).
For example, VccB=3.3 volts, VccA=2.5 volts and VthN=1.0 volts give VccB−VthN=3.3−1.0=2.3 volts at the terminal A.
The second known one-way system, however, suffers from output-voltage fluctuation due to variation in threshold level VthN of the transistor N1. For example, variation of ±0.2 volts in threshold level VthN causes output-voltage fluctuation in the range from 2.1 to 2.5 volts. The lowest output voltage of 2.1 volts is 0.4 volts lower than VccA of 2.5 volts, thus causing a static current passing through the first-stage circuit component connected to the terminal A.
Such a static current passing through the first-stage component will be discussed with reference to FIG. 24.
The first-stage circuit component of the first logic circuit is an inverter in FIG. 24.
In a one-way system from the terminals B to A, an output signal of 2.1 volts at the terminal A turns on a transistor N2 of the inverter. Also turned on, but not completely, is a transistor P1 of the inverter due to a gate-to-source voltage Vgs of 0.4 volts, the difference between 2.5 volts (VccA level) and 2.1 volts. The transistor P1 causes flow of static current passing through the transistor N2.
On the contrary, in a one-way system from the terminals A to B, voltages appearing at the terminal A is 2.5 volts and 3.3−1=2.3 volts (gate voltage to the transistor N1) at the terminal B, respectively, like the one-way system from the terminals B to A.
Another first-stage circuit component, if connected to the terminal B, will have a gate-to-source voltage Vgs of 3.3−2.3=1 volts to its P-channel transistor, thus suffering from more static current.
As discussed above, the signal-level converter having an N-channel transistor only is simple in structure, but, still disadvantageous in the effects of threshold-voltage fluctuation in the N-channel transistor and also static current passing through the next-stage circuitry.
In summary, the known signal-level converter used in the two-way system described above requires many components, thus becoming bulk in chip size. In addition, the terminal DIR for deciding signal-transfer (input/output) direction causes complexity of control.
The one-way system does not require the terminal DIR, thus not so complex in control compared to the two-way system, but, still becoming bulk in chip size when the known signal-level converter is used.
Moreover, a switching transistor for the known signal-level converter in the one-way system causes flow of static current to pass through transistors, etc., of the first-stage circuit component due to variation in threshold level of the switching transistor.